As shown in, for example, JP-A-2002-374181 (Patent Document 1), digital wireless receivers of the prior art are fabricated by existing integrated circuit production technology to reduce the number of expensive off-chip elements such as surface acoustic wave filters, thereby realizing both low cost and low power consumption.
FIG. 1 is a block diagram of a digital wireless receiver of the prior art. As shown in FIG. 1, this digital wireless receiver of the prior art comprises: antenna 100, radio frequency band selection filter 101, amplifier 102, sample-hold circuit 105, I-phase band-pass filter 108, Q-phase band-pass filter 109, I-phase analog/digital converter 110, and Q-phase analog/digital converter 111.
Antenna 100 receives a radio signal. Radio frequency band selection filter 101 selects only the band used in communication from among the various frequency components contained in the received signal. Amplifier 102 amplifies the output signal of the radio frequency band selection filter 101. Sample-hold circuit 105 samples the output signal of amplifier 102 and then holds for a predetermined time period to produce a discrete time signal. Sample-hold circuit 105 includes: I-phase sampling switch 103 and Q-phase sampling switch 104 that are turned on and off in accordance with sampling clocks supplied from I-phase sampling clock distribution system 114 and Q-phase sampling clock distribution system 115, respectively, to sample the input signal at a predetermined time interval; and I-phase sampling capacity module 106 and Q-phase sampling capacity module 107 for holding each signal level of the I-phase and Q-phase, respectively, that are sampled for the predetermined time period. I-phase band-pass filter 108 and Q-phase band-pass filter 109 each eliminate unnecessary aliasing components that are generated by discretization of signals and unnecessary frequency components such as undesired channels from the output of I-phase sampling capacity module 106 and Q-phase sampling capacity module 107, respectively, of sample-hold circuit 105. I-phase analog/digital converter 110 and Q-phase analog/digital converter 111 each convert the output signals of I-phase band-pass filter 108 and Q-phase band-pass filter 109, respectively, from analog signals to digital signals. It is to be noted that a plurality of RF band-pass filters may be cascode-connected to increase the selectivity of the frequency band, and the digital wireless receiver is not limited to the configuration shown in FIG. 1.
Operation of the above-described digital wireless receiver of the prior art will now be described. First, a radio signal is converted to an electrical signal by antenna 100. Due to attenuation undergone when being propagated through space, the converted electrical signal is extremely weak, and the radio signal is further mixed with, for example, other signals used in communication apparatus. As a result, the receiver must amplify the signal to a level that allows demodulation while suppressing to the utmost the occurrence of, for example, thermal noise, and must further eliminate unnecessary mixed signals to selectively extract only the signal that is used in communication. To this end, radio frequency band selection filter 101 that selectively passes the frequency band used in radio communication and amplifier 102 are connected in the section that follows antenna 100 and respectively serve the roles of frequency selection and signal amplification.
However, due to the band-pass characteristics of radio frequency band selection filter 101 that is in common use, undesired frequency components typically remain at the time that a signal is supplied from radio frequency band selection filter 101 and amplifier 102. Further filtering must therefore be carried out to eliminate undesired frequency components. The frequency selection that is carried out in the latter stage for this purpose eliminates signals of bands extremely close to the frequency band of the desired signal. This calls for a filter wherein a band that signals are passed and a band that signals are blocked, are close, i.e., a filter having a high cut-off characteristic. Filters having higher cut-off characteristics also have greater filter circuit scale, and even among filters having the same cut-off characteristic, filters having higher center frequency of the passed frequency band have greater scale. For this reason, increasing frequency selectivity while suppressing circuit scale necessitates the implementation of frequency conversion.
In order to achieve lower power consumption while suppressing a further expansion of circuit scale in this frequency conversion, the receiver of the prior art shown in FIG. 1 comprises sample-hold circuit 105, I-phase band-pass filter 108, and Q-phase band-pass filter 109. A description will now be given of the reasons for carrying out frequency conversion by means of sample-hold circuit 105, I-phase band-pass filter 108, and Q-phase band-pass filter 109. When a signal continuous over time and having a particular frequency band is converted to a discrete time signal at fixed intervals by using sample-hold circuit 105, other frequency components may be reproduced from this discrete time signal that are outside the original input signal. Frequency components contained in a discrete signal that are outside the frequency band of the original input signal are termed “aliases.” Generally, any time function in which the frequency band is limited within W is uniquely expressed by means of a sampling value at a discrete time for each ½W. When a signal is sampled at a time interval greater than this time interval, aliases overlap, lowering the signal-to-noise ratio of the modulated signal. This is a fundamental theory of digital signal processing known as “Shannon's sampling theorem” that calls for sampling at a sampling frequency that is at least twice the frequency band value of a modulated signal. This “sampling theorem” is a basic premise for dealing with discrete signals and will not be particularly mentioned in the following discussion. If only the desired band is selected/extracted by a digital filter from among the multiplicity of alias components that are generated by the discretization of the output signal of amplifier 102 at the sampling frequency demanded from this sampling theorem, the center frequency of the band can be converted without damaging the baseband signal.
In this example of the prior art, an input modulated signal is sampled by turning I-phase sampling switch 103 and Q-phase sampling switch 104 on and off by means of I-phase sampling clocks and Q-phase sampling clocks that are 90° out of phase with I-phase sampling clocks, respectively, and the results are held for a predetermined time interval in I-phase sampling capacity 106 and Q-phase sampling capacity 107, respectively. This operation allows the input signal to be separated into an I-component and Q-component and converted to discrete time signals. The desired frequency band is selected/extracted for the I and Q components by means of I-phase band-pass filter 108 and Q-phase band-pass filter 109 that are connected to the output of sample-hold circuit 105. The signals are then demodulated to digital baseband signals by I-phase analog/digital converter 110 and Q-phase analog/digital converter 111, respectively. The digital baseband signals that have been demodulated are provided to I-phase physical layer signal processor 112 and Q-phase physical layer signal processor 112, respectively. The above-described sequence of operations repeats as long as the input of packet signals continues.
As described in JP-A-2003-338771 (Patent Document 2), one example of the prior art aims for lower power consumption by shutting down the circuit while packet communication is not being carried out. However, because no mention is made regarding techniques for quickly completing demodulation when carrying out demodulation for packet transmission and reception, all circuits must be operated during all symbol intervals. As a result, there is no example in the prior art for lowering power consumption by plans such as shutting down circuits during symbol intervals.
Patent Document 1: JP-A-2002-374181
Patent Document 2: JP-A-2003-338771